Recently, with an advance in the degree of integration of large-scale integrated circuits (LSIs), it has been possible to integrate a large-scale logical circuit formed of large capacity memories and digital circuits, operation circuits, and analog circuits on a 1 cm.times.1 cm semiconductor chip, for example. In the near future, it is expected that so-called system-on-silicon, in which the whole system is integrated using such a chip, will be realized.
Japanese Patent Laid-Open No. 212185 (1996) discloses an example in which a large capacity memory and a CPU (Central Processing Unit), which is a large scale logic circuit, are integrated on the same chip. In this example, the memory is provided on the edge portion of the chip while logic circuits such as a CPU, peripheral circuits and interface circuits are arranged on the central portion of the chip. When the memory is provided only at the edge portion of a chip, as described in the prior art, there is the problem that the degree of freedom of a chip layout is lowered. Particularly, in an ASIC (Application Specific Integrated Circuit) realizing a function desired by users using a memory core, a CPU core, and the like, the decrease in the degree of freedom of the chip layout leads to an increased chip area.
The present inventor has studied the chip layout shown in FIG. 2, in which a dynamic memory and logical circuits are integrated. The semiconductor chip CHIP comprises logical blocks BLK1 and BLK2 each formed of digital circuits, and a dynamic memory DM disposed between the logical blocks BLK1 and BLK2, and other elements. The logical block BLK1 includes a logical circuit LC1 while the logical block BLK2 includes a logical circuit LC2. The blocks are connected to each other with the wiring WR1. Other wiring connections besides WR1 are omitted for simplification.
Logical blocks BLK1 and BLK2 are arranged on both sides of the dynamic memory DM. Hence, when an output terminal of the logic circuit LC1 is connected to an input terminal of the logic circuit LC2, its shortest route crosses over the dynamic memory DM. However, upon taking into consideration the influence on signals on WR1 caused by noises generated from the dynamic memory DM as well as the change in potential influenced upon the dynamic memory DM due to wiring WR1, the wiring must be detoured around the dynamic memory DM to ensure stable operation. However, with a large number of wiring lines connecting the logical block BLK1 with the logical block BLK2, such a detouring procedure causes an increase in wiring area, thus increasing the chip area. Moreover the problem arises that the wiring length becomes long so that the wiring delay makes it difficult to operate at high speed.
Of course, if only the wiring WR1 is preferentially considered, the length of the wiring WR1 can be shortened by closely arranging the blocks BLK1 and BLK2. However, since there are many wiring layers between logical blocks and a dynamic memory and many wiring layers between logical blocks and bonding pads, in addition to the wiring WR1 between blocks, the layout of functional blocks cannot generally be determined only by considering a specific wiring. As a result, memories or analog circuits must be arranged between a plurality of logic blocks or between logic blocks and bonding pads to be connected to each other with wirings.
Japanese Patent Laid-Open No. 121349 (1990) discloses that a cell using a circuit, internally including a node, which performs a dynamic operation is covered with a grounded wiring layer while a wiring between cells is formed over the grounded wiring layer. Moreover, Japanese Patent Laid-open No. 152968 (1991) discloses that a metal layer connected to the ground potential is formed between the wiring layer within a cell and the wiring layer between cells. However, these references do not teach the integration of dynamic memories and logical circuit blocks on a single semiconductor substrate. Moreover, the references do not teach the passing of wiring provided between logical blocks over the upper portion of the dynamic memory nor the necessity of doing so. In the prior art, the metal wiring layer, where a shielding metal is provided, is used only for shielding. The references do not teach that the metal wiring layer is used to pass signal wirings for a logical circuit.